V. Narayanan and 25 others, “Band-Edge High-Performance high-k/Metal Gate n-MOSFETs using Cap Layers Containing Group IIA and IIIB Elemens with Gate-First Processing for 45 nm and Beyond”, 2006 Symposium on VLSI Technology Digest of Technical Papers (Non-patent Document 1) discloses a technology for simultaneously reducing, with good balance, the threshold voltages (more precisely, the absolute value thereof) of both an n-MISFET (Metal Insulator Semiconductor Field Effect Transistor) and a p-MISFET, each having a High-k gate insulating film. In this technology, on the High-k gate insulating films of the respective regions, another metal or metal oxide is formed and the component thereof is introduced into the High-k gate insulating films.
T. Morooka and 13 others, “Suppression of Anomalous Threshold Voltage Increase with Area Scaling for Mg- or La-incorporated High-k/Metal Gate nMOSFETs in Deep Scaled Region”, 2010 Symposium on VLSI Technology Digest of Technical Papers (Non-patent Document 2) discloses a technology for controlling the threshold voltages of an n-MISFET and p-MISFET. In this technology, the processed end portion of a High-k gate insulating film is extended to the end portion of an offset sidewall in order to prevent the concentration of an additive component, which has been introduced into the High-k gate insulating film, from decreasing due to the diffusion caused later by high-temperature heat treatment.